VMOVDQU8
DATAXFER AVX512BW_128 x86_64
VMOVDQU8 is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category DATAXFER. This page lists its 9 encoding forms, distinguished by opcode bytes: 6F, 7F.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512
MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u8
XED_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512
MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u8
XED_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512
MEM0:w:zd:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu8
XED_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512
REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8
XED_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512
REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8
XED_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512
REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8
XED_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512
REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8
XED_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512
REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8
XED_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512
REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8