VMOVRSQ

DATAXFER AVX10_MOVRS_128 x86_64

VMOVRSQ is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category DATAXFER. This page lists its 3 encoding forms, distinguished by opcode byte: 6F.

Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.

XED_VMOVRSQ_XMMu64_MASKmskw_MEMu64_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64
X86_LEGACY 6F /r AVX10_MOVRS_128
XED_VMOVRSQ_YMMu64_MASKmskw_MEMu64_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64
X86_LEGACY 6F /r AVX10_MOVRS_256
XED_VMOVRSQ_ZMMu64_MASKmskw_MEMu64_AVX512
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64
X86_LEGACY 6F /r AVX10_MOVRS_512