VMOVSD
DATAXFER AVX512F_SCALAR x86_64
VMOVSD is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category DATAXFER. This page lists its 6 encoding forms, distinguished by opcode bytes: 10, 11.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512
MEM0:w:q:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64
XED_VMOVSD_X86_LEGACY_ONEBYTE_10_103788
REG0=XMM_R():w:dq:f64 MEM0:r:q:f64
XED_VMOVSD_X86_LEGACY_ONEBYTE_11_265512
MEM0:w:q:f64 REG0=XMM_R():r:q:f64
XED_VMOVSD_XMMdq_XMMdq_XMMq_10 VMOVSD_XMMdq_XMMdq_XMMq_11
REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 REG0=XMM_B():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_R():r:q:f64
XED_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512
REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64
XED_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64