VMOVUPD
REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64 REG0=XMM_B():w:dq:f64 REG1=XMM_R():r:dq:f64 REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64 REG0=YMM_B():w:qq:f64 REG1=YMM_R():r:qq:f64
x86_64 X86_LEGACY DATAXFER AVX source: xed
XED_VMOVUPD_XMMdq_XMMdq_10 VMOVUPD_XMMdq_XMMdq_11 VMOVUPD_YMMqq_YMMqq_10 VMOVUPD_YMMqq_YMMqq_11
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 10 10 11 11 10 10 11 11 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| vex_l | 1 |
| exception_class | avx-type-4M |
| cpl | 3 |
| raw_encoding | VV1 0x10 V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0x10 V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0x11 V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0x11 V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0x10 V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0x10 V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0x11 V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0x11 V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] |
Operands (16)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | w | W | EXPLICIT | MODRM_REG | |
| 1 | MEM0 | MEM | f64 | R | EXPLICIT | MODRM_RM | |
| 2 | REG1 | REG | w | W | EXPLICIT | MODRM_REG | |
| 3 | REG2 | REG | f64 | R | EXPLICIT | MODRM_REG | |
| 4 | MEM1 | MEM | w | W | EXPLICIT | MODRM_RM | |
| 5 | REG3 | REG | f64 | R | EXPLICIT | MODRM_REG | |
| 6 | REG4 | REG | w | W | EXPLICIT | MODRM_REG | |
| 7 | REG5 | REG | f64 | R | EXPLICIT | MODRM_REG | |
| 8 | REG6 | REG | w | W | EXPLICIT | MODRM_REG | |
| 9 | MEM2 | MEM | f64 | R | EXPLICIT | MODRM_RM | |
| 10 | REG7 | REG | w | W | EXPLICIT | MODRM_REG | |
| 11 | REG8 | REG | f64 | R | EXPLICIT | MODRM_REG | |
| 12 | MEM3 | MEM | w | W | EXPLICIT | MODRM_RM | |
| 13 | REG9 | REG | f64 | R | EXPLICIT | MODRM_REG | |
| 14 | REG10 | REG | w | W | EXPLICIT | MODRM_REG | |
| 15 | REG11 | REG | f64 | R | EXPLICIT | MODRM_REG |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.