VMOVW
DATAXFER AVX512_MOVZXC_128 x86_64
VMOVW is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category DATAXFER. This page lists its 7 encoding forms, distinguished by opcode bytes: 6E, 7E.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VMOVW_GPR32f16_XMMf16_AVX512
REG0=GPR32_B():w:d:f16 REG1=XMM_R3():r:dq:f16
XED_VMOVW_MEMf16_XMMf16_AVX512
MEM0:w:wrd:f16 REG0=XMM_R3():r:dq:f16
XED_VMOVW_MEMu16_XMMu16_AVX512_MOVZXC
MEM0:w:wrd:u16 REG0=XMM_R3():r:dq:u16
XED_VMOVW_XMMf16_GPR32f16_AVX512
REG0=XMM_R3():w:dq:f16 REG1=GPR32_B():r:d:f16
XED_VMOVW_XMMf16_MEMf16_AVX512
REG0=XMM_R3():w:dq:f16 MEM0:r:wrd:f16
XED_VMOVW_XMMu16_MEMu16_AVX512_MOVZXC
REG0=XMM_R3():w:dq:u16 MEM0:r:wrd:u16
XED_VMOVW_XMMu16_XMMu16_AVX512_MOVZXC
REG0=XMM_R3():w:dq:u16 REG1=XMM_B3():r:dq:u16