VMREAD

MEM0:w:q REG0=GPR64_R():r REG0=GPR64_B():w REG1=GPR64_R():r MEM0:w:d REG0=GPR32_R():r REG0=GPR32_B():w REG1=GPR32_R():r

x86_64 X86_LEGACY VTX VTX source: xed

XED_VMREAD_X86_LEGACY_0F_78_67905

Encoding

encoding_kindX86_LEGACY
opcode_bytes78 0F 78 0F 78 0F 78
opcode_map0F
mandatory_prefix-
has_modrmTrue
requires_modelong
attributesRING0
cpl0
raw_encoding0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH() 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH() 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH() 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()

Operands (8)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 MEM0 MEM w W EXPLICIT MODRM_RM
1 REG0 REG R EXPLICIT MODRM_REG
2 REG1 REG w W EXPLICIT MODRM_REG
3 REG2 REG R EXPLICIT MODRM_REG
4 MEM1 MEM w W EXPLICIT MODRM_RM
5 REG3 REG R EXPLICIT MODRM_REG
6 REG4 REG w W EXPLICIT MODRM_REG
7 REG5 REG R EXPLICIT MODRM_REG

Flag effects (6)

CF = WRITE PF = SET_0 AF = SET_0 ZF = WRITE SF = SET_0 OF = SET_0

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.