VP2INTERSECTD
AVX512_VP2INTERSECT AVX512_VP2INTERSECT_128 x86_64
VP2INTERSECTD is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512_VP2INTERSECT. This page lists its 6 encoding forms, distinguished by opcode byte: 68.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512
REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
XED_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512
REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u32 REG2=XMM_B3():r:dq:u32
XED_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512
REG0=MASK_R():w:mskw:MULTIDEST2 REG1=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
XED_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512
REG0=MASK_R():w:mskw:MULTIDEST2 REG1=YMM_N3():r:qq:u32 REG2=YMM_B3():r:qq:u32
XED_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512
REG0=MASK_R():w:mskw:MULTIDEST2 REG1=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
XED_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512
REG0=MASK_R():w:mskw:MULTIDEST2 REG1=ZMM_N3():r:zu32 REG2=ZMM_B3():r:zu32