VPABSB
AVX512 AVX512BW_128 x86_64
VPABSB is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512. This page lists its 8 encoding forms, distinguished by opcode byte: 1C.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPABSB_X86_LEGACY_ONEBYTE_1C_118563
REG0=XMM_R():w:dq:u8 MEM0:r:dq:i8 REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:i8
XED_VPABSB_X86_LEGACY_ONEBYTE_1C_961901
REG0=YMM_R():w:qq:u8 MEM0:r:qq:i8 REG0=YMM_R():w:qq:u8 REG1=YMM_B():r:qq:i8
XED_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512
REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8
XED_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512
REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
XED_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512
REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8
XED_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512
REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8
XED_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512
REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:i8
XED_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512
REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi8