VPACKSSDW
AVX512 AVX512BW_128 x86_64
VPACKSSDW is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512. This page lists its 8 encoding forms, distinguished by opcode byte: 6B.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPACKSSDW_X86_LEGACY_ONEBYTE_6B_208576
REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32
XED_VPACKSSDW_X86_LEGACY_ONEBYTE_6B_84363
REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32
XED_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512
REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
XED_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512
REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32
XED_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512
REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
XED_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512
REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32
XED_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512
REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR
XED_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512
REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32