VPBLENDW
AVX AVX x86_64
VPBLENDW is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX. This page lists its 4 encoding forms, distinguished by opcode byte: 0E.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
X86_VPBLENDW_X86_LEGACY_ONEBYTE_0E_167550
ymm, ymm, ymm/m256, imm8
X86_VPBLENDW_X86_LEGACY_ONEBYTE_0E_830127
xmm, xmm, xmm/m128, imm8
XED_VPBLENDW_X86_LEGACY_ONEBYTE_0E_400454
REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 IMM0:r:b
XED_VPBLENDW_X86_LEGACY_ONEBYTE_0E_924886
REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 IMM0:r:b