VPBROADCASTB
BROADCAST AVX512BW_128 x86_64
VPBROADCASTB is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category BROADCAST. This page lists its 10 encoding forms, distinguished by opcode bytes: 78, 7A.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPBROADCASTB_X86_LEGACY_ONEBYTE_78_483172
REG0=XMM_R():w:dq:u8 MEM0:r:b:u8 EMX_BROADCAST_1TO16_8 REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:b:u8 EMX_BROADCAST_1TO16_8 REG0=YMM_R():w:qq:u8 MEM0:r:b:u8 EMX_BROADCAST_1TO32_8 REG0=YMM_R():w:qq:u8 REG1=XMM_B():r:b:u8 EMX_BROADCAST_1TO32_8
XED_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512
REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO16_8
XED_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512
REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO16_8
XED_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512
REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO16_8
XED_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512
REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO32_8
XED_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512
REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO32_8
XED_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512
REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO32_8
XED_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512
REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO64_8
XED_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512
REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO64_8
XED_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512
REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO64_8