VPBROADCASTD
BROADCAST AVX512F_128 x86_64
VPBROADCASTD is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category BROADCAST. This page lists its 10 encoding forms, distinguished by opcode bytes: 58, 7C.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPBROADCASTD_X86_LEGACY_ONEBYTE_58_787035
REG0=XMM_R():w:dq:u32 MEM0:r:d:u32 EMX_BROADCAST_1TO4_32 REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u32 EMX_BROADCAST_1TO4_32 REG0=YMM_R():w:qq:u32 MEM0:r:d:u32 EMX_BROADCAST_1TO8_32 REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:d:u32 EMX_BROADCAST_1TO8_32
XED_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512
REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32
XED_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512
REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO4_32
XED_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512
REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO4_32
XED_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512
REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32
XED_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512
REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO8_32
XED_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512
REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO8_32
XED_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512
REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32 REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32
XED_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512
REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO16_32
XED_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512
REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO16_32