VPBROADCASTQ
BROADCAST AVX512F_128 x86_64
VPBROADCASTQ is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category BROADCAST. This page lists its 10 encoding forms, distinguished by opcode bytes: 59, 7C.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPBROADCASTQ_X86_LEGACY_ONEBYTE_59_159183
REG0=XMM_R():w:dq:u64 MEM0:r:q:u64 EMX_BROADCAST_1TO2_64 REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u64 EMX_BROADCAST_1TO2_64 REG0=YMM_R():w:qq:u64 MEM0:r:q:u64 EMX_BROADCAST_1TO4_64 REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:q:u64 EMX_BROADCAST_1TO4_64
XED_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO2_64
XED_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO2_64
XED_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO2_64
XED_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO4_64
XED_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO4_64
XED_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO4_64
XED_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO8_64
XED_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO8_64
XED_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO8_64