VPBROADCASTW
BROADCAST AVX512BW_128 x86_64
VPBROADCASTW is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category BROADCAST. This page lists its 10 encoding forms, distinguished by opcode bytes: 79, 7B.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPBROADCASTW_X86_LEGACY_ONEBYTE_79_56857
REG0=XMM_R():w:dq:u16 MEM0:r:w:u16 EMX_BROADCAST_1TO8_16 REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:w:u16 EMX_BROADCAST_1TO8_16 REG0=YMM_R():w:qq:u16 MEM0:r:w:u16 EMX_BROADCAST_1TO16_16 REG0=YMM_R():w:qq:u16 REG1=XMM_B():r:w:u16 EMX_BROADCAST_1TO16_16
XED_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512
REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO8_16
XED_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512
REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO8_16
XED_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512
REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO8_16
XED_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512
REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO16_16
XED_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512
REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO16_16
XED_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512
REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO16_16
XED_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512
REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO32_16
XED_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512
REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO32_16
XED_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512
REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO32_16