VPCMPEQD
AVX512 AVX512F_128 x86_64
8 encoding forms.
XED_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
XED_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
XED_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
XED_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
XED_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
XED_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
XED_VPCMPEQD_X86_LEGACY_ONEBYTE_76_487136
REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32
XED_VPCMPEQD_X86_LEGACY_ONEBYTE_76_923864
REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32