VPCMPESTRM64

REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP

x86_64 X86_LEGACY STTNI AVX source: xed

XED_VPCMPESTRM64_X86_LEGACY_ONEBYTE_60_153142

Encoding

encoding_kindX86_LEGACY
opcode_bytes60 60
opcode_mapONEBYTE
mandatory_prefix-
has_modrmTrue
vex_l0
imm_size_bytes1
requires_modelong
exception_classavx-type-4
cpl3
raw_encodingVV1 0x60 VL128 V66 V0F3A NOVSR mode64 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()

Operands (12)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 REG0 REG R EXPLICIT MODRM_REG
1 MEM0 MEM R EXPLICIT MODRM_RM
2 IMM0 IMM b R EXPLICIT IMM
3 REG1 REG (=RAX) R SUPPRESSED MODRM_REG
4 REG2 REG (=RDX) R SUPPRESSED MODRM_REG
5 REG3 REG (=XMM0) w W SUPPRESSED MODRM_REG
6 REG4 REG R EXPLICIT MODRM_REG
7 REG5 REG R EXPLICIT MODRM_REG
8 IMM1 IMM b R EXPLICIT IMM
9 REG6 REG (=RAX) R SUPPRESSED MODRM_REG
10 REG7 REG (=RDX) R SUPPRESSED MODRM_REG
11 REG8 REG (=XMM0) w W SUPPRESSED MODRM_REG

Flag effects (6)

CF = WRITE PF = SET_0 AF = SET_0 ZF = WRITE SF = WRITE OF = WRITE

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.