VPCMPW
AVX512 AVX512BW_128 x86_64
VPCMPW is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512. This page lists its 6 encoding forms, distinguished by opcode byte: 3F.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 IMM0:r:b
XED_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 IMM0:r:b
XED_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 IMM0:r:b
XED_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 IMM0:r:b
XED_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 IMM0:r:b
XED_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 IMM0:r:b