VPCOMPRESSD

COMPRESS AVX512F_128 x86_64

6 encoding forms.

XED_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512
MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32
X86_LEGACY 8B /r AVX512F_128
XED_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512
MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32
X86_LEGACY 8B /r AVX512F_256
XED_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512
MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32
X86_LEGACY 8B /r AVX512F_512
XED_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512
REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32
X86_LEGACY 8B /r AVX512F_128
XED_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512
REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32
X86_LEGACY 8B /r AVX512F_256
XED_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512
REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32
X86_LEGACY 8B /r AVX512F_512