VPCONFLICTQ
CONFLICT AVX512CD_128 x86_64
6 encoding forms.
XED_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
XED_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
XED_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
XED_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
XED_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
XED_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64