VPDPBSSDS
VEX AVX_VNNI_INT8 x86_64
10 encoding forms.
XED_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512
REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:4i8 MEM0:r:vv:4i8:TXT=BCASTSTR
XED_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512
REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:4i8 REG3=XMM_B3():r:dq:4i8
XED_VPDPBSSDS_XMMi32_XMM4i8_MEM4i8
REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4i8 MEM0:r:dq:4i8
XED_VPDPBSSDS_XMMi32_XMM4i8_XMM4i8
REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4i8 REG2=XMM_B():r:dq:4i8
XED_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512
REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:4i8 MEM0:r:vv:4i8:TXT=BCASTSTR
XED_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512
REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:4i8 REG3=YMM_B3():r:qq:4i8
XED_VPDPBSSDS_YMMi32_YMM4i8_MEM4i8
REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4i8 MEM0:r:qq:4i8
XED_VPDPBSSDS_YMMi32_YMM4i8_YMM4i8
REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4i8 REG2=YMM_B():r:qq:4i8
XED_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512
REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z4i8 MEM0:r:vv:4i8:TXT=BCASTSTR
XED_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512
REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z4i8 REG3=ZMM_B3():r:z4i8