VPDPBUUDS
VEX AVX_VNNI_INT8 x86_64
10 encoding forms.
XED_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512
REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:4u8 MEM0:r:vv:4u8:TXT=BCASTSTR
XED_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512
REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:4u8 REG3=XMM_B3():r:dq:4u8
XED_VPDPBUUDS_XMMu32_XMM4u8_MEM4u8
REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:4u8 MEM0:r:dq:4u8
XED_VPDPBUUDS_XMMu32_XMM4u8_XMM4u8
REG0=XMM_R():rw:dq:u32 REG1=XMM_N():r:dq:4u8 REG2=XMM_B():r:dq:4u8
XED_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512
REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:4u8 MEM0:r:vv:4u8:TXT=BCASTSTR
XED_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512
REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:4u8 REG3=YMM_B3():r:qq:4u8
XED_VPDPBUUDS_YMMu32_YMM4u8_MEM4u8
REG0=YMM_R():rw:qq:u32 REG1=YMM_N():r:qq:4u8 MEM0:r:qq:4u8
XED_VPDPBUUDS_YMMu32_YMM4u8_YMM4u8
REG0=YMM_R():rw:qq:u32 REG1=YMM_N():r:qq:4u8 REG2=YMM_B():r:qq:4u8
XED_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512
REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z4u8 MEM0:r:vv:4u8:TXT=BCASTSTR
XED_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512
REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z4u8 REG3=ZMM_B3():r:z4u8