VPDPWSSDS
VEX AVX_VNNI x86_64
VPDPWSSDS is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category VEX. This page lists its 10 encoding forms, distinguished by opcode byte: 53.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512
REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:vv:u32:TXT=BCASTSTR
XED_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512
REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:u32
XED_VPDPWSSDS_XMMi32_XMMu32_MEMu32
REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32
XED_VPDPWSSDS_XMMi32_XMMu32_XMMu32
REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32
XED_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512
REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:vv:u32:TXT=BCASTSTR
XED_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512
REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:u32
XED_VPDPWSSDS_YMMi32_YMMu32_MEMu32
REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32
XED_VPDPWSSDS_YMMi32_YMMu32_YMMu32
REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32
XED_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512
REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:vv:u32:TXT=BCASTSTR
XED_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512
REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zu32