VPDPWSUD
REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:2i16 REG2=XMM_B():r:dq:2u16
x86_64 X86_LEGACY VEX AVX_VNNI_INT16 source: xed
XED_VPDPWSUD_XMMi32_XMM2i16_XMM2u16
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | D2 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| vex_l | 0 |
| exception_class | avx-type-4 |
| cpl | 3 |
| raw_encoding | VV1 0xD2 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 |
Operands (3)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | RW | EXPLICIT | MODRM_REG | ||
| 1 | REG1 | REG | R | EXPLICIT | MODRM_REG | ||
| 2 | REG2 | REG | R | EXPLICIT | MODRM_REG |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.