VPDPWUSD
REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2u16 MEM0:r:vv:2i16:TXT=BCASTSTR
x86_64 X86_LEGACY VEX AVX512_VNNI_INT16_256 source: xed
XED_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | D2 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| vex_l | 1 |
| attributes | BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION |
| exception_class | AVX512-E4 |
| cpl | 3 |
| raw_encoding | EVV 0xD2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 ESIZE_32_BITS() NELEM_FULL() |
Operands (4)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | RW | EXPLICIT | MODRM_REG | ||
| 1 | REG1 | REG | R | EXPLICIT | MODRM_REG | ||
| 2 | REG2 | REG | R | EXPLICIT | MODRM_REG | ||
| 3 | MEM0 | MEM | R | EXPLICIT | MODRM_RM |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.