VPDPWUSDS
VEX AVX_VNNI_INT16 x86_64
10 encoding forms.
XED_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512
REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2u16 MEM0:r:vv:2i16:TXT=BCASTSTR
XED_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512
REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2u16 REG3=XMM_B3():r:dq:2i16
XED_VPDPWUSDS_XMMi32_XMM2u16_MEM2i16
REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:2u16 MEM0:r:dq:2i16
XED_VPDPWUSDS_XMMi32_XMM2u16_XMM2i16
REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:2u16 REG2=XMM_B():r:dq:2i16
XED_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512
REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2u16 MEM0:r:vv:2i16:TXT=BCASTSTR
XED_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512
REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2u16 REG3=YMM_B3():r:qq:2i16
XED_VPDPWUSDS_YMMi32_YMM2u16_MEM2i16
REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:2u16 MEM0:r:qq:2i16
XED_VPDPWUSDS_YMMi32_YMM2u16_YMM2i16
REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:2u16 REG2=YMM_B():r:qq:2i16
XED_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512
REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2u16 MEM0:r:vv:2i16:TXT=BCASTSTR
XED_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512
REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2u16 REG3=ZMM_B3():r:z2i16