VPERMIL2PD

REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 IMM0:r:b REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 IMM0:r:b REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 IMM0:r:b REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 IMM0:r:b REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 IMM0:r:b REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 IMM0:r:b

x86_64 X86_LEGACY XOP XOP source: xed

XED_VPERMIL2PD_X86_LEGACY_ONEBYTE_49_309852

Encoding

encoding_kindX86_LEGACY
opcode_bytes49 49 49 49 49 49 49 49
opcode_mapONEBYTE
mandatory_prefix-
has_modrmTrue
vex_l1
attributesAMDONLY
cpl3
raw_encodingVV1 0x49 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() VV1 0x49 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() VV1 0x49 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() VV1 0x49 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() VV1 0x49 VL128 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() VV1 0x49 VL128 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() VV1 0x49 VL256 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() VV1 0x49 VL256 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()

Operands (40)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 REG0 REG w W EXPLICIT MODRM_REG
1 REG1 REG f64 R EXPLICIT MODRM_REG
2 MEM0 MEM f64 R EXPLICIT MODRM_RM
3 REG2 REG f64 R EXPLICIT MODRM_REG
4 IMM0 IMM b R EXPLICIT IMM
5 REG3 REG w W EXPLICIT MODRM_REG
6 REG4 REG f64 R EXPLICIT MODRM_REG
7 REG5 REG f64 R EXPLICIT MODRM_REG
8 REG6 REG f64 R EXPLICIT MODRM_REG
9 IMM1 IMM b R EXPLICIT IMM
10 REG7 REG w W EXPLICIT MODRM_REG
11 REG8 REG f64 R EXPLICIT MODRM_REG
12 MEM1 MEM f64 R EXPLICIT MODRM_RM
13 REG9 REG f64 R EXPLICIT MODRM_REG
14 IMM2 IMM b R EXPLICIT IMM
15 REG10 REG w W EXPLICIT MODRM_REG
16 REG11 REG f64 R EXPLICIT MODRM_REG
17 REG12 REG f64 R EXPLICIT MODRM_REG
18 REG13 REG f64 R EXPLICIT MODRM_REG
19 IMM3 IMM b R EXPLICIT IMM
20 REG14 REG w W EXPLICIT MODRM_REG
21 REG15 REG f64 R EXPLICIT MODRM_REG
22 REG16 REG f64 R EXPLICIT MODRM_REG
23 MEM2 MEM f64 R EXPLICIT MODRM_RM
24 IMM4 IMM b R EXPLICIT IMM
25 REG17 REG w W EXPLICIT MODRM_REG
26 REG18 REG f64 R EXPLICIT MODRM_REG
27 REG19 REG f64 R EXPLICIT MODRM_REG
28 REG20 REG f64 R EXPLICIT MODRM_REG
29 IMM5 IMM b R EXPLICIT IMM
30 REG21 REG w W EXPLICIT MODRM_REG
31 REG22 REG f64 R EXPLICIT MODRM_REG
32 REG23 REG f64 R EXPLICIT MODRM_REG
33 MEM3 MEM f64 R EXPLICIT MODRM_RM
34 IMM6 IMM b R EXPLICIT IMM
35 REG24 REG w W EXPLICIT MODRM_REG
36 REG25 REG f64 R EXPLICIT MODRM_REG
37 REG26 REG f64 R EXPLICIT MODRM_REG
38 REG27 REG f64 R EXPLICIT MODRM_REG
39 IMM7 IMM b R EXPLICIT IMM

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.