VPERMILPD

REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:u64 REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:u64 REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:u64 REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:u64 REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 IMM0:r:b REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b

x86_64 X86_LEGACY AVX512 AVX source: xed

XED_VPERMILPD_X86_LEGACY_ONEBYTE_0D_853745

Encoding

encoding_kindX86_LEGACY
opcode_bytes0D 0D 0D 0D 05 05 05 05
opcode_mapONEBYTE
mandatory_prefix-
has_modrmTrue
vex_l1
imm_size_bytes1
exception_classavx-type-6
cpl3
raw_encodingVV1 0x0D VL128 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0x0D VL128 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0x0D VL256 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0x0D VL256 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0x05 VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() VV1 0x05 VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() VV1 0x05 VL256 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() VV1 0x05 VL256 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()

Operands (24)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 REG0 REG w W EXPLICIT MODRM_REG
1 REG1 REG f64 R EXPLICIT MODRM_REG
2 MEM0 MEM R EXPLICIT MODRM_RM
3 REG2 REG w W EXPLICIT MODRM_REG
4 REG3 REG f64 R EXPLICIT MODRM_REG
5 REG4 REG R EXPLICIT MODRM_REG
6 REG5 REG w W EXPLICIT MODRM_REG
7 REG6 REG f64 R EXPLICIT MODRM_REG
8 MEM1 MEM R EXPLICIT MODRM_RM
9 REG7 REG w W EXPLICIT MODRM_REG
10 REG8 REG f64 R EXPLICIT MODRM_REG
11 REG9 REG R EXPLICIT MODRM_REG
12 REG10 REG w W EXPLICIT MODRM_REG
13 MEM2 MEM f64 R EXPLICIT MODRM_RM
14 IMM0 IMM b R EXPLICIT IMM
15 REG11 REG w W EXPLICIT MODRM_REG
16 REG12 REG f64 R EXPLICIT MODRM_REG
17 IMM1 IMM b R EXPLICIT IMM
18 REG13 REG w W EXPLICIT MODRM_REG
19 MEM3 MEM f64 R EXPLICIT MODRM_RM
20 IMM2 IMM b R EXPLICIT IMM
21 REG14 REG w W EXPLICIT MODRM_REG
22 REG15 REG f64 R EXPLICIT MODRM_REG
23 IMM3 IMM b R EXPLICIT IMM

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.