VPERMPS
AVX512 AVX512F_256 x86_64
VPERMPS is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512. This page lists its 5 encoding forms, distinguished by opcode byte: 16.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPERMPS_X86_LEGACY_ONEBYTE_16_712147
REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
XED_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
XED_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
XED_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
XED_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32