VPERMT2B
AVX512_VBMI AVX512_VBMI_128 x86_64
VPERMT2B is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512_VBMI. This page lists its 6 encoding forms, distinguished by opcode byte: 7D.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
XED_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
XED_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
XED_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
XED_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
XED_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8