VPERMT2W

AVX512 AVX512BW_128 x86_64

6 encoding forms.

XED_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
X86_LEGACY 7D /r AVX512BW_128
XED_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
X86_LEGACY 7D /r AVX512BW_128
XED_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
X86_LEGACY 7D /r AVX512BW_256
XED_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
X86_LEGACY 7D /r AVX512BW_256
XED_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
X86_LEGACY 7D /r AVX512BW_512
XED_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
X86_LEGACY 7D /r AVX512BW_512