VPEXPANDB

EXPAND AVX512_VBMI2_128 x86_64

6 encoding forms.

XED_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512
REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8
X86_LEGACY 62 /r AVX512_VBMI2_128
XED_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512
REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8
X86_LEGACY 62 /r AVX512_VBMI2_128
XED_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512
REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8
X86_LEGACY 62 /r AVX512_VBMI2_256
XED_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512
REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8
X86_LEGACY 62 /r AVX512_VBMI2_256
XED_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512
REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8
X86_LEGACY 62 /r AVX512_VBMI2_512
XED_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512
REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8
X86_LEGACY 62 /r AVX512_VBMI2_512