VPHSUBSW

AVX AVX x86_64

VPHSUBSW is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX. This page lists its 4 encoding forms, distinguished by opcode byte: 07.

Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.

X86_VPHSUBSW_X86_LEGACY_ONEBYTE_07_154510

xmm, xmm, xmm/m128

X86_LEGACY 07 /r AVX

X86_VPHSUBSW_X86_LEGACY_ONEBYTE_07_292152

ymm, ymm, ymm/m256

X86_LEGACY 07 /r AVX2

XED_VPHSUBSW_X86_LEGACY_ONEBYTE_07_190338

REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16

X86_LEGACY 07 07 /r AVX2

XED_VPHSUBSW_X86_LEGACY_ONEBYTE_07_980541

REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16

X86_LEGACY 07 07 /r AVX