VPINSRB

AVX512 AVX512BW_128N x86_64

VPINSRB is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512. This page lists its 3 encoding forms, distinguished by opcode byte: 20.

Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.

XED_VPINSRB_X86_LEGACY_ONEBYTE_20_90102
REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:b:u8 IMM0:r:b REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=VGPR32_B():r:d:u8 IMM0:r:b
X86_LEGACY 20 20 /r AVX
XED_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512
REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 REG2=GPR32_B():r:d:u8 IMM0:r:b
X86_LEGACY 20 /r AVX512BW_128N
XED_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512
REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 MEM0:r:b:u8 IMM0:r:b
X86_LEGACY 20 /r AVX512BW_128N