VPINSRW
AVX512 AVX512BW_128N x86_64
VPINSRW is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512. This page lists its 3 encoding forms, distinguished by opcode byte: C4.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPINSRW_X86_LEGACY_ONEBYTE_C4_422590
REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:w:u16 IMM0:r:b REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=VGPR32_B():r:d:u16 IMM0:r:b
XED_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512
REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 REG2=GPR32_B():r:d:u16 IMM0:r:b
XED_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512
REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 MEM0:r:wrd:u16 IMM0:r:b