VPLZCNTQ

CONFLICT AVX512CD_128 x86_64

6 encoding forms.

XED_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
X86_LEGACY 44 /r AVX512CD_128
XED_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
X86_LEGACY 44 /r AVX512CD_128
XED_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
X86_LEGACY 44 /r AVX512CD_256
XED_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
X86_LEGACY 44 /r AVX512CD_256
XED_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
X86_LEGACY 44 /r AVX512CD_512
XED_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
X86_LEGACY 44 /r AVX512CD_512