VPMADD52LUQ
REG0=XMM_R():rw:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64
x86_64 X86_LEGACY AVX_IFMA AVX_IFMA source: xed
XED_VPMADD52LUQ_XMMu64_XMMu64_XMMu64
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | B4 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| vex_l | 0 |
| exception_class | avx-type-4 |
| cpl | 3 |
| raw_encoding | VV1 0xB4 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 |
Operands (3)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | RW | EXPLICIT | MODRM_REG | ||
| 1 | REG1 | REG | R | EXPLICIT | MODRM_REG | ||
| 2 | REG2 | REG | R | EXPLICIT | MODRM_REG |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.