VPMOVQB

DATAXFER AVX512F_128 x86_64

6 encoding forms.

XED_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512
MEM0:w:wrd:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
X86_LEGACY 32 /r AVX512F_128
XED_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512
MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
X86_LEGACY 32 /r AVX512F_256
XED_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512
MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
X86_LEGACY 32 /r AVX512F_512
XED_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512
REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64
X86_LEGACY 32 /r AVX512F_128
XED_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512
REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64
X86_LEGACY 32 /r AVX512F_256
XED_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512
REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64
X86_LEGACY 32 /r AVX512F_512