VPMOVSWB
DATAXFER AVX512BW_128 x86_64
VPMOVSWB is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category DATAXFER. This page lists its 6 encoding forms, distinguished by opcode byte: 20.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512
MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i16
XED_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512
MEM0:w:dq:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i16
XED_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512
MEM0:w:qq:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi16
XED_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512
REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i16
XED_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512
REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i16
XED_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512
REG0=YMM_B3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi16