VPMOVSXBD
DATAXFER AVX512F_128 x86_64
8 encoding forms.
XED_VPMOVSXBD_X86_LEGACY_ONEBYTE_21_870076
REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:d:i8 REG0=XMM_R():w:dq:i32 MEM0:r:d:i8
XED_VPMOVSXBD_X86_LEGACY_ONEBYTE_21_902975
REG0=YMM_R():w:qq:i32 REG1=XMM_B():r:q:i8 REG0=YMM_R():w:qq:i32 MEM0:r:q:i8
XED_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512
REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8
XED_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512
REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
XED_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512
REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8
XED_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512
REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
XED_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512
REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8
XED_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512
REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8