VPMOVSXBW
DATAXFER AVX512BW_128 x86_64
VPMOVSXBW is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category DATAXFER. This page lists its 8 encoding forms, distinguished by opcode byte: 20.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPMOVSXBW_X86_LEGACY_ONEBYTE_20_50342
REG0=YMM_R():w:qq:i16 REG1=XMM_B():r:dq:i8 REG0=YMM_R():w:qq:i16 MEM0:r:dq:i8
XED_VPMOVSXBW_X86_LEGACY_ONEBYTE_20_51443
REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:q:i8 REG0=XMM_R():w:dq:i16 MEM0:r:q:i8
XED_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512
REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8
XED_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512
REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
XED_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512
REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8
XED_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512
REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
XED_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512
REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8
XED_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512
REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8