VPMOVUSWB

DATAXFER AVX512BW_128 x86_64

6 encoding forms.

XED_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512
MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16
X86_LEGACY 10 /r AVX512BW_128
XED_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512
MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16
X86_LEGACY 10 /r AVX512BW_256
XED_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512
MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16
X86_LEGACY 10 /r AVX512BW_512
XED_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512
REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16
X86_LEGACY 10 /r AVX512BW_128
XED_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512
REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16
X86_LEGACY 10 /r AVX512BW_256
XED_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512
REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16
X86_LEGACY 10 /r AVX512BW_512