VPMOVUSWB
DATAXFER AVX512BW_128 x86_64
VPMOVUSWB is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category DATAXFER. This page lists its 6 encoding forms, distinguished by opcode byte: 10.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512
MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16
XED_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512
MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16
XED_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512
MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16
XED_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512
REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16
XED_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512
REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16
XED_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512
REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16