VPMOVZXBD

DATAXFER AVX512F_128 x86_64

VPMOVZXBD is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category DATAXFER. This page lists its 8 encoding forms, distinguished by opcode byte: 31.

Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.

XED_VPMOVZXBD_X86_LEGACY_ONEBYTE_31_276063

REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:q:u8 REG0=YMM_R():w:qq:u32 MEM0:r:q:u8

X86_LEGACY 31 31 /r AVX2

XED_VPMOVZXBD_X86_LEGACY_ONEBYTE_31_42327

REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u8 REG0=XMM_R():w:dq:u32 MEM0:r:d:u8

X86_LEGACY 31 31 /r AVX

XED_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512

REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8

X86_LEGACY 31 /r AVX512F_128

XED_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512

REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8

X86_LEGACY 31 /r AVX512F_128

XED_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512

REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8

X86_LEGACY 31 /r AVX512F_256

XED_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512

REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8

X86_LEGACY 31 /r AVX512F_256

XED_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512

REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8

X86_LEGACY 31 /r AVX512F_512

XED_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512

REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8

X86_LEGACY 31 /r AVX512F_512