VPMOVZXBQ
DATAXFER AVX512F_128 x86_64
VPMOVZXBQ is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category DATAXFER. This page lists its 8 encoding forms, distinguished by opcode byte: 32.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPMOVZXBQ_X86_LEGACY_ONEBYTE_32_338268
REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:d:u8 REG0=YMM_R():w:qq:u64 MEM0:r:d:u8
XED_VPMOVZXBQ_X86_LEGACY_ONEBYTE_32_732649
REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:w:u8 REG0=XMM_R():w:dq:u64 MEM0:r:w:u8
XED_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512
REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:i8
XED_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512
REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
XED_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512
REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8
XED_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512
REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
XED_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512
REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8
XED_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512
REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8