VPMOVZXWQ

DATAXFER AVX512F_128 x86_64

VPMOVZXWQ is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category DATAXFER. This page lists its 8 encoding forms, distinguished by opcode byte: 34.

Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.

XED_VPMOVZXWQ_X86_LEGACY_ONEBYTE_34_522084

REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:q:u16 REG0=YMM_R():w:qq:u64 MEM0:r:q:u16

X86_LEGACY 34 34 /r AVX2

XED_VPMOVZXWQ_X86_LEGACY_ONEBYTE_34_853258

REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:d:u16 REG0=XMM_R():w:dq:u64 MEM0:r:d:u16

X86_LEGACY 34 34 /r AVX

XED_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512

REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i16

X86_LEGACY 34 /r AVX512F_128

XED_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512

REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16

X86_LEGACY 34 /r AVX512F_128

XED_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512

REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16

X86_LEGACY 34 /r AVX512F_256

XED_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512

REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16

X86_LEGACY 34 /r AVX512F_256

XED_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512

REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16

X86_LEGACY 34 /r AVX512F_512

XED_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512

REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16

X86_LEGACY 34 /r AVX512F_512