VPMULDQ
AVX512 AVX512F_128 x86_64
8 encoding forms.
XED_VPMULDQ_X86_LEGACY_ONEBYTE_28_407332
REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32
XED_VPMULDQ_X86_LEGACY_ONEBYTE_28_839447
REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32
XED_VPMULDQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512
REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR
XED_VPMULDQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512
REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64
XED_VPMULDQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512
REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR
XED_VPMULDQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512
REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64
XED_VPMULDQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512
REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR
XED_VPMULDQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512
REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64