VPMULLQ

AVX512 AVX512DQ_128 x86_64

6 encoding forms.

XED_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
X86_LEGACY 40 /r AVX512DQ_128
XED_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
X86_LEGACY 40 /r AVX512DQ_128
XED_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
X86_LEGACY 40 /r AVX512DQ_256
XED_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
X86_LEGACY 40 /r AVX512DQ_256
XED_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
X86_LEGACY 40 /r AVX512DQ_512
XED_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
X86_LEGACY 40 /r AVX512DQ_512