VPROLD
AVX512 AVX512F_128 x86_64
6 encoding forms.
XED_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512
REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
XED_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512
REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b
XED_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512
REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
XED_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512
REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b
XED_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512
REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
XED_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512
REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b