VPROLVD

AVX512 AVX512F_128 x86_64

6 encoding forms.

XED_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
X86_LEGACY 15 /r AVX512F_128
XED_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
X86_LEGACY 15 /r AVX512F_128
XED_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
X86_LEGACY 15 /r AVX512F_256
XED_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
X86_LEGACY 15 /r AVX512F_256
XED_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
X86_LEGACY 15 /r AVX512F_512
XED_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
X86_LEGACY 15 /r AVX512F_512