VPSHUFBITQMB
AVX512 AVX512_BITALG_128 x86_64
VPSHUFBITQMB is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512. This page lists its 6 encoding forms, distinguished by opcode byte: 8F.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u8
XED_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u8
XED_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:qq:u8
XED_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u8
XED_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:zd:u8
XED_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu8