VPSHUFHW
AVX512 AVX512BW_128 x86_64
VPSHUFHW is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512. This page lists its 8 encoding forms, distinguished by opcode byte: 70.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPSHUFHW_X86_LEGACY_ONEBYTE_70_570821
REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b
XED_VPSHUFHW_X86_LEGACY_ONEBYTE_70_888707
REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 IMM0:r:b REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b
XED_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512
REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b
XED_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512
REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b
XED_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512
REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b
XED_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512
REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b
XED_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512
REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b
XED_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512
REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b